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FDB20AN06A0 / FDP20AN06A0
June 2003
FDB20AN06A0 / FDP20AN06A0
N-Channel PowerTrench(R) MOSFET 60V, 45A, 20m
Features
* r DS(ON) = 17m (Typ.), VGS = 10V, ID = 45A * Qg(tot) = 15nC (Typ.), VGS = 10V * Low Miller Charge * Low QRR Body Diode * UIS Capability (Single Pulse and Repetitive Pulse) * Qualified to AEC Q101
Formerly developmental type 82547
Applications
* Motor / Body Load Control * ABS Systems * Powertrain Management * Injection Systems * DC-DC converters and Off-line UPS * Distributed Power Architectures and VRMs * Primary Switch for 12V and 24V systems
DRAIN (FLANGE)
D
SOURCE DRAIN GATE SOURCE GATE
G
TO-220AB
FDP SERIES
TO-263AB
FDB SERIES
DRAIN (FLANGE)
S
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 10V) Continuous (Tamb = 25oC, VGS = 10V, R JA = 43oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy ( Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 45 32 9 Figure 4 50 90 0.60 -55 to 175 A A A A mJ W W/oC
o
Ratings 60 20
Units V V
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-220, TO-263 Thermal Resistance Junction to Ambient TO-220, TO-263 ( Note 2) Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 1.67 62 43
oC/W o o
C/W C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
Package Marking and Ordering Information
Device Marking FDB20AN06A0 FDP20AN06A0 Device FDB20AN06A0 FDP20AN06A0 Package TO-263AB TO-220AB Reel Size 330mm Tube Tape Width 24mm N/A Quantity 800 units 50 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
B VDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V V DS = 50V VGS = 0V VGS = 20V TC = 150oC 60 1 250 100 V A nA
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 45A, VGS = 10V ID = 45A, VGS = 10V, TJ = 175oC 2 0.017 0.039 4 0.020 0.047 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge V DS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 30V ID = 45A Ig = 1.0mA 950 185 60 15 2 6 4 4.5 19 2.6 pF pF pF nC nC nC nC nC
Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time V DD = 30V, ID = 45A VGS = 10V, RGS = 20 11 98 23 33 164 84 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 45A ISD = 22A ISD = 45A, dISD/dt = 100A/s ISD = 45A, dISD/dt = 100A/s 1.25 1.0 32 25 V V ns nC
Notes: 1: Starting TJ = 25C, L = 80H, I AS = 36A. 2: Pulse width = 100s.
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
Typical Characteristics TC = 25C unless otherwise noted
1.2 50
POWER DISSIPATION MULTIPLIER
1.0 ID, DRAIN CURRENT (A) 0 25 50 75 100 150 175 40
0.8
30
0.6
20
0.4
0.2
10
0 125 TC , CASE TEMPERATURE (o C)
0 25 50 75 100 125 (o C) 150 175
TC, CASE TEMPERATURE
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t , RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
Figure 3. Normalized Maximum Transient Thermal Impedance
600 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A)
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 175 - TC 150
100
40 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
Figure 4. Peak Current Capability
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
Typical Characteristics TC = 25C unless otherwise noted
1000 10s ID, DRAIN CURRENT (A) 100 100s 300 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
100
1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 SINGLE PULSE TJ = MAX RATED TC = 25o C 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 10ms
STARTING TJ = 25oC 10
DC
STARTING TJ = 150oC 1 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
100 VGS = 20V 80 ID, DRAIN CURRENT (A) VGS = 10V VGS = 7V
100
80 ID , DRAIN CURRENT (A)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V TJ = -55 C
o
TJ = 175oC
60
60
40 TJ = 25oC 20
40
VGS = 6V TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
20 VGS = 5V
0 4 5 6 7 8 VGS , GATE TO SOURCE VOLTAGE (V) 9
0 0 1 2 3 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
17.5 DRAIN TO SOURCE ON RESISTANCE(m) NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 17.0 2.5
Figure 8. Saturation Characteristics
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0
16.5
1.5
16.0 VGS = 10V 15.5 0 10 20 30 ID, DRAIN CURRENT (A) 40 50
1.0
VGS = 10V, ID = 45A 0.5 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (o C) 160 200
Figure 9. Drain to Source On Resistance vs Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
Typical Characteristics TC = 25C unless otherwise noted
1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.10 1.15 ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.05
0.8
1.00
0.6
0.95
0.4 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
0.90 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
2000 CISS = CGS + CGD 1000 C, CAPACITANCE (pF) COSS CDS + C GD C RSS = CGD
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 30V 8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 45A ID = 9A 0 3 6 9 12 15
100 VGS = 0V, f = 1MHz 40 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 60
2
0 Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Current
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS
+
IAS 0.01 0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS VDD L VGS VDS Qg(TOT) VGS
VGS = 10V
+
VDD DUT Ig(REF) VGS = 2V 0
Qgs2
Qg(TH) Qgs Ig(REF) 0 Qgd
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P D M = ----------------------------R JA
80 RJA = 26.51+ 19.84/(0.262+Area) EQ.2 RJA = 26.51+ 128/(1.69+Area) EQ.3 60 RJA (o C/W) 40 20 0.1 (0.645) 1 (6.45) AREA, TOP COPPER AREA in2 (cm2 ) 10 (64.5)
(EQ. 1)
In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA
Figure 21. Thermal Resistance vs Mounting Pad Area
= 26.51 + ------------------------------------
19.84 ( 0.262 + Area )
(EQ. 2)
Area in Inches Squared
R
JA
= 26.51 + ---------------------------------
128 ( 1.69 + Area )
(EQ. 3)
Area in Centimeters Squared
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
PSPICE Electrical Model
.SUBCKT FDP20AN06A0 2 1 3 ; rev April 2003 Ca 12 8 4.4e-10 Cb 15 14 4.4e-10 Cin 6 8 9.2e-10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 67.2 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 6.3e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.5e-9 RLgate 1 9 63 RLdrain 2 5 10 RLsource 3 7 25 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1e-3 Rgate 9 20 4.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 10e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),2.7))} .MODEL DbodyMOD D (IS=3.8E-12 N=1.06 RS=4e-3 TRS1=2.4e-3 TRS2=1.1e-6 + CJO=6.8e-10 M=0.53 TT=2.3e-8 XTI=3.9) .MODEL DbreakMOD D (RS=1.8 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=2.7e-10 IS=1e-30 N=10 M=0.44) .MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=4.7 T_ABS=25) .MODEL MstroMOD NMOS (VTO=4.34 KP=35 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MweakMOD NMOS (VTO=3.27 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=47 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=9e-4 TC2=1e-7) .MODEL RdrainMOD RES (TC1=6e-3 TC2=8e-5) .MODEL RSLCMOD RES (TC1=1e-3 TC2=3.5e-5) .MODEL RsourceMOD RES (TC1=9e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.1e-3 TC2=-1.3e-5) .MODEL RvtempMOD RES (TC1=-3e-3 TC2=1e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
CA S1A 12 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 GATE 1 RLGATE CIN 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE RBREAK 18 RVTEMP 19 VBAT + 22 7 SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED LDRAIN DPLCAP 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
(c)2003 Fairchild Semiconductor Corporation
+
DBODY
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
SABER Electrical Model
rev April 2003 template FDP20AN06A0 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=3.8e-12,nl=1.06,rs=4e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=6.8e-10,m=0.53,tt=2.3e-8,xti=3.9) dp..model dbreakmod = (rs=1.8,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=2.7e-10,isl=10e-30,nl=10,m=0.44) m..model mmedmod = (type=_n,vto=3.8,kp=2,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.34,kp=35,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.27,kp=0.03,is=1e-30, tox=1,rs=0.1) LDRAIN DPLCAP 5 DRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5) 2 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8) 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5) RLDRAIN RSLC1 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2) 51 c.ca n12 n8 = 4.4e-10 RSLC2 c.cb n15 n14 = 4.4e-10 ISCL c.cin n6 n8 = 9.2e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 67.2 GATE 1 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1
12 LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6 MSTRO CIN 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
RLGATE
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
l.lgate n1 n9 = 6.3e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.5e-9 res.rlgate n1 n9 = 63 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 25
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u ,temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u ,temp=m_temp res.rbreak n17 n18 = 1, tc1=9e-4,tc2=1e-7 res.rdrain n50 n16 = 1e-3, tc1=6e-3,tc2=8e-5 res.rgate n9 n20 = 4.7 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=3.5e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 10e-3, tc1=9e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.1e-3,tc2=-1.3e-5 res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 2.7)) } }
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
FDB20AN06A0 / FDP20AN06A0
PSPICE Thermal Model
REV 23 April 2003 FDP20AN06A0T CTHERM1 TH 6 1.8e-3 CTHERM2 6 5 8.0e-3 CTHERM3 5 4 9.0e-3 CTHERM4 4 3 1.1e-2 CTHERM5 3 2 1.2e-2 CTHERM6 2 TL 2.0e-2 RTHERM1 TH 6 3.0e-2 RTHERM2 6 5 1.0e-1 RTHERM3 5 4 1.4e-1 RTHERM4 4 3 2.3e-1 RTHERM5 3 2 4.1e-1 RTHERM6 2 TL 4.2e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDP20AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1.8e-3 ctherm.ctherm2 6 5 =8.0e-3 ctherm.ctherm3 5 4 =9.0e-3 ctherm.ctherm4 4 3 =1.1e-2 ctherm.ctherm5 3 2 =1.2e-2 ctherm.ctherm6 2 tl =2.0e-2 rtherm.rtherm1 th 6 =3.0e-2 rtherm.rtherm2 6 5 =1.0e-1 rtherm.rtherm3 5 4 =1.4e-1 rtherm.rtherm4 4 3 =2.3e-1 rtherm.rtherm5 3 2 =4.1e-1 rtherm.rtherm6 2 tl =4.2e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2003 Fairchild Semiconductor Corporation
FDB20AN06A0 / FDP20AN06A0 Rev. B
TRADEMARKS
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DISCLAIMER
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Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I3

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